This invention relates generally to sample and hold circuits. Such circuits may also be called sample-hold amplifiers, track/hold amplifiers, or the like. More specifically, the present invention relates to sample and hold (S/H) circuits which exhibit both a fast acquisition time and a low droop rate. The acquisition time parameter may alternatively be called sample time, and the droop rate parameter may alternatively be called a drift rate.
A S/H circuit receives an input signal which typically changes in time. A S/H circuit typically operates in two modes. In a sample mode the S/H circuit acts as an amplifier. Thus, an output signal directly corresponds to the input signal. While in the sampling mode, a hold capacitor within the S/H circuit tracks or acquires a voltage which corresponds to the input signal. In a hold mode the output of the S/H circuit becomes isolated from the input, and the output remains at a voltage level which corresponds to the voltage acquired by the hold capacitor.
Acquisition time and droop rate are two particularly important parameters in S/H circuits. The acquisition time represents the amount of time required for the hold capacitor to accurately charge to a voltage level which corresponds to the input signal. Droop rate refers to the change in the output signal over time when the S/H circuit is in the hold mode. Generally, shorter acquisition times and lower droops are desired.
A representative S/H circuit uses an input buffer which receives the input signal and drives an input to a sample switch. The sample switch has an output which drives the hold capacitor and an input to an output buffer. The output buffer provides the output signal.
Those skilled in the art recognize that various design factors may be considered to improve both acquisition time and droop rate. For example, choosing input buffers having higher slew rates and higher current supplying capabilities, choosing hold capacitors which have smaller values, and allowing imprecise acquisition by the hold capacitor tend to decrease the S/H circuit acquisition time. Likewise, lower droop rates can be obtained by choosing capacitors having lower leakages and higher capacitance values, output buffers having low input bias currents, sample switches with low leakage currents, and using guard bands and compensation capacitors.
Although prior art S/H circuits may exhibit fast acquisition times or low droop rates, they tend to improve one parameter at the expense of degrading other parameters. For example, one technique known to improve droop rate requires the sample switch to have no voltage across it when the S/H circuit is in the hold mode. However, prior art implementions of this technique add an additional switch in series with the sample switch. Thus, on-resistance of the series connected switches increases, resistance in series with the hold capacitor increases, and acquisition time suffers.
Alternatively, fast acquisition time S/H circuits tend to apply a voltage across the sample switch when the S/H circuit is in the hold mode. Thus, sample switch leakage current increases and the resulting droop rate may be higher than is desired.